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| TDA7312 DIGITAL CONTROLLED STEREO AUDIO PROCESSOR ADVANCE DATA INPUT MULTIPLEXER: - 4 STEREO INPUTS FOUR SELECTABLE ADDRESSES TWO DIGITAL CONTROL OUTPUTS INPUT AND OUTPUT FOR EXTERNAL EQUALIZER OR NOISE REDUCTION SYSTEM VOLUME CONTROL IN 1.25dB STEPS TREBLE AND BASS CONTROL TWO SPEAKER ATTENUATORS: - INDEPENDENT SPEAKERS CONTROL IN 1.25dB STEPS - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2C BUS DESCRIPTION The TDA7312 is a volume, tone (bass and treble) balance (Left/Right) processor for quality audio applications. SDIP30 ORDERING NUMBER: TDA7312 Control is accomplished by serial I2C bus microprocessor interface. The AC signal setting is obtained by resistor networks and switches combined with operationalamplifiers. Thanks to the used BIPOLAR/CMOS Tecnology, Low Distortion, Low Noise and Low DC stepping are obtained. PIN CONNECTION (Top view) February 1994 1/13 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. TDA7312 TEST CIRCUIT THERMAL DATA Symbol R th j-pins Description Thermal Resistance Junction-pins max SDIP30 85 Unit C/W ABSOLUTE MAXIMUM RATINGS Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.2 0 to 70 -40 to 150 Unit V C C QUICK REFERENCE DATA Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz Volume Control 1.25dB step 2db step 1.25dB step -78.75 -14 -38.75 100 Bass and Treble Control Fader and Balance Control Mute Attenuation Parameter Min. 6 2 0.01 106 103 0 +14 0 0.1 Typ. 9 Max. 10 Unit V Vrms % dB dB dB dB dB dB 2/13 TDA7312 BLOCK DIAGRAM 3/13 TDA7312 ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K, RG = 600, all controls flat (G = 0), f = 1KHz unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VS IS SVR Supply Voltage Supply Current Ripple Rejection 60 6 9 8 80 10 11 V mA dB INPUT SELECTORS R II VCL SIN RL eIN Input Resistance Clipping Level Input Separation (2) Output Load resistance Input Noise Input 1, 2, 3 35 2 80 2 2 50 2.5 100 70 K Vrms dB K V VOLUME CONTROL RIV C RANGE AVMIN AVMAX ASTEP EA ET VDC Input Resistance Control Range Min. Attenuation Max. Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps adjacent attenuation steps From 0dB to Av max 0 0.5 Av = 0 to -20dB Av = -20 to -60dB 20 70 -1 70 0.5 -1.25 -3 33 75 0 75 1.25 0 50 80 1 80 1.75 1.25 2 2 3 7.5 k dB dB dB dB dB dB dB mV mV SPEAKER ATTENUATORS Crange SSTEP EA AMUTE VDC Control Range Step Resolution Attenuation set error Output Mute Attenuation DC Steps adjacent att. steps from 0 to mute 80 100 0 1 3 10 35 0.5 37.5 1.25 40 1.75 1.5 dB dB dB dB mV mV BASS CONTROL (1) Gb BSTEP RB Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut +12 1 34 +14 2 44 +16 3 58 dB dB K TREBLE CONTROL (1) Gt TSTEP Control Range Step Resolution Max. Boost/cut +13 1 +14 2 +15 3 dB dB DIGITAL OUTPUTS VCESAT Ileak I leakage VOUT = Low IC =1mA VOUT = VS 0.2 0.3 10 V A 4/13 TDA7312 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit AUDIO OUTPUTS VOCL RL CL ROUT VOUT Clipping Level Output Load Resistance Output Load Capacitance Output resistance DC Voltage Level 30 4.2 75 4.5 d = 0.3% 2 2 10 120 4.8 2.5 Vrms K nF V GENERAL e NO Output Noise BW = 20-20KHz, flat output muted all gains = 0dB A curve all gains = 0dB S/N d Signal to Noise Ratio Distortion all gains = 0dB; VO = 1Vrms AV = 0, VIN = 1Vrms AV = -20dB VIN = 1Vrms VIN = 0.3Vrms 80 AV = 0 to -20dB -20 to -60 dB 2.5 5 3 106 0.01 0.09 0.04 103 0 0 1 2 0.1 0.3 V V V dB % % % dB dB dB 15 Sc Channel Separation left/right Total Tracking error BUS INPUTS VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA 3 -5 +5 0.4 1 V V A V ADDRESS PIN (Internal 50K pull down resistor). Notes: SDA, SCL, DIG OUT 1, DIG OUT 2 Pins are high impedance when VS =0 (1) Bass and Treble response see attached diagram (fig.16). The center frequency and quality of the resonance behaviour can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network (2) The selected input is grounded thru the 2.2F capacitor. Figure 1: Noise vs. Volume/Gain Settings Figure 2: Signal to Noise Ratio vs. Volume Setting 5/13 TDA7312 Figure 3: Distortion & Noise vs. Frequency Figure 4: Distortion & Noise vs. Frequency Figure 5: Distortion vs. Load Resistance Figure 6: Channel Separation (L R) vs. Frequency Figure 7: Input Separation (L1 L2, L3, L4) vs. Frequency Figure 8: Supply Voltage Rejection vs. Frequency 6/13 TDA7312 Figure 9: Output Clipping Level vs. Supply Voltage Figure 10: Quiescent Current vs. Supply Voltage Figure 11: SupplyCurrent vs. Temperature Figure 12: Bass Resistance vs. Temperature Figure 13: Typical Tone Response (with the ext. components indicated in the test circuit) 7/13 TDA7312 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7312 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 14, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.15 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 14: Data Validity on the I2CBUS knowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 16). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Figure 15: Timing Diagram of I2CBUS Figure 16: Acknowledge on the I2CBUS 8/13 TDA7312 SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7312 address (the 8th bit of the byte must be 0). The TDA7312 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) TDA7312 ADDRESS MSB S 1 0 first byte 0 0 LSB MSB DATA LSB ACK MSB DATA LSB ACK P 1 ADDR ADDR 0 ACK 2 1 Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop SOFTWARE SPECIFICATION Chip address 1 MSB 0 0 0 1 ADDR ADDR 0 2 1 LSB ADDR2 ADDR1 0 0 1 1 0 1 0 1 88 HEX 8A HEX 8C HEX 8E HEX CHIP ADDRESS DATA BYTES MSB 0 1 1 0 0 0 0 0 0 1 1 1 B2 0 1 0 1 1 B1 B1 B1 D2 0 1 B0 B0 B0 D1 C3 C3 A2 A2 A2 S2 C2 C2 A1 A1 A1 S1 C1 C1 LSB A0 A0 A0 S0 C0 C0 FUNCTION Volume control Speaker ATT L Speaker ATT R Audio switch Bass control Treble control Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Sx = Input Selector; D X = Dig Out Pins 9/13 TDA7312 SOFTWARE SPECIFICATION (continued) DATA BYTES (detailed description) Volume MSB 0 0 B2 B1 B0 A2 0 0 0 0 1 1 1 1 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 A2 A1 0 0 1 1 0 0 1 1 A1 LSB A0 0 1 0 1 0 1 0 1 A0 FUNCTION Volume 1.25dB steps 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 Volume 10dB steps 0 -10 -20 -30 -40 -50 -60 -70 For example a volume of -45dB is given by: 00100100 Speaker Attenuators MSB 1 1 0 0 0 1 B1 B1 B0 B0 A2 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 A1 A1 0 0 1 1 0 0 1 1 LSB A0 A0 0 1 0 1 0 1 0 1 FUNCTION Speaker L Speaker R 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 -10 -20 -30 Mute For example attenuation of 25dB on speaker R is given by: 10110100 10/13 TDA7312 Audio Switch MSB 0 1 0 D2 D1 S2 1 1 1 1 0 1 0 1 S1 0 0 1 1 LSB S0 0 1 0 1 FUNCTION Audio Switch Stereo 1 Stereo 2 Stereo 3 Stereo 4 DIG. DIG. DIG. DIG. OUT 1 = 0 OUT 1 = 1 OUT 2 = 0 OUT 2 = 1 Bass and Treble 0 0 1 1 1 1 0 1 C3 C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 C1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 C0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Bass Treble -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 C3 = Sign For example Bass at -10dB is obtained by the following 8 bit string: 01100010 Status at Power on Reset Volume = 78.75dB Treble = Bass = +2dB Spkrs Attenuators = Mute Input = Stereo 1 Dig. OUT 1 = Dig. OUT 2 = 1 11/13 TDA7312 SDIP30 PACKAGE MECHANICAL DATA DIM. MIN. A A1 A2 B B1 C D E E1 e e1 L M S 0.31 2.54 0.51 3.05 0.36 0.76 0.20 27.43 10.16 8.38 3.81 0.46 0.99 0.25 27.94 10.41 8.64 1.78 10.16 3.30 3.81 0.10 4.57 0.56 1.40 0.36 28.45 11.05 9.40 mm TYP. MAX. 5.08 0.020 0.12 0.014 0.030 0.008 1.08 0.400 0.330 0.15 0.018 0.039 0.01 1.10 0.410 0.340 0.070 0.400 0.13 0.15 0.18 0.022 0.055 0.014 1.12 0.435 0.370 MIN. inch TYP. MAX. 0.20 0(min.), 15(max.) 0.012 12/13 TDA7312 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 2 13/13 |
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